LITERATURE row, making it infeasible in real

            LITERATURE SURVEYABSTRACTSystem-level detection of DRAM failures offers a variety ofsystem enhancements, such as better reliability, energy, and performance. System-leveldetection is challenging for DRAM failures that depend on the data content of neighboringcells (known as data-dependent failures). All these optimizations depend on accurately detecting every possibledata-dependent failure that could occur with any content in DRAM.

The goals inthese works are to decouple the detection and mitigation of data-dependentfailures from physical DRAM organization such that it is possible to detectfailures without knowledge of DRAM internals. MEMCON is a memory content-baseddetection and mitigation mechanism for data-dependent failures in DRAM. MEMCONdoes not detect every possible data-dependent failure.

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Instead, it detects andmitigates failures that occur with the current content in memory while theprograms are running in the system. DRAM vendors internally remap the system-level address space.Therefore, testing data-dependent failures using neighboring system-leveladdresses does not actually test the cells that are physically adjacent. Inthis work, we argue that one promising way to uncover data-dependent failuresin the system is to determine the location of physically neighboring cells inthe system address space. Unfortunately such a test takes 49 days to detectneighboring addresses even in a single memory row, making it infeasible in realsystems. PARBOR is an efficient system-level technique that determines thelocations of the physically neighboring DRAM cells in the system address spaceand uses this information to detect data-dependent failures.

  This is the first work that solves thechallenge of detecting data-dependent failures in DRAM in the presence ofDRAM-internal scrambling of system-level addresses.       INTRODUCTIONThe continued scaling of DRAM process technology has enabledhigher density DRAM by placing smaller memory cells close to each other.Unfortunately, the close proximity of cells exacerbates cell-to-cellinterference, making cells susceptible to failures.

A prominent type ofinterference failure occurs depending on the data content in neighboring cells.Such failures are called data-dependent failures. These failures are inherentto DRAM design as they are caused by the electromagnetic coupling between wiresused to access DRAM cells. Manufacturers detect these failures by exhaustivelytesting neighboring DRAM cells with data patterns that introduce enoughcell-to-cell interference to cause failures and then either remap the failedbits or discard the faulty chips to avoid the failures. Therefore, thesefailures can significantly affect the yield and manufacturing cost of DRAMchips. As DRAM cells get smaller, more cells fail due to cell-to-cellinterference, posing a significant challenge to DRAM scaling.

Prior worksproposed to detect and mitigate these failures in the field, while the systemis under operation, as a way to ensure correct DRAM operation while still beingable to continue the scaling of process technology. Such system level detectionand mitigation of DRAM failures provides better reliability, performance, andenergy efficiency in future memory systems. Unfortunately, detection andmitigation of data dependent failures face two major challenges. First, thedetection of data-dependent failures is closely tied to internal DRAMorganization, which is different in each chip and usually not exposed to thesystem.

Without the exact knowledge of the internal design of a DRAM chip, itis not possible to detect all failures. Second, detecting all possibledata-dependent failures, which constitute a very large number of failures, istime consuming. It is expected that systems will have to detect and mitigate aneven larger number of data dependent failures in the future as cells becomemore vulnerable to interference with DRAM scaling.The goal of the first is to decouple the detection andmitigation of data-dependent failures from DRAM internals and design a low overheadmechanism that can be implemented in the system without requiring any knowledgeabout the specifics of internal DRAM design. So MEMCON is introducedwhich is a memory content-based detection and mitigation mechanism fordata-dependent failures in DRAM.While the system and applications are running, MEMCON detects failureswith the current content in memory.

These detected failures are mitigated usinga high refresh rate for rows that contain the failing cells. MEMCONsignificantly reduces the mitigation cost as the number of failures withcurrent content is less than the total number of failures with every possiblecombination of data content.  Even though asystem-level detection and mitigation technique offers better reliability,performance, and energy efficiency, such a technique faces a major unresolvedchallenge in DRAM failure detection. An efficient test method based on two keyideas is developed.

The first key idea leverages the observation that cells exhibitvariability in the way they get affected by cell-to-cell interference. Second key ideaenables us to detect both neighboring locations with multiple simplelinear tests. This method is known as PArallel Recursive neighBOR(PARBOR) testing, which detects the locations of physically neighboringcells efficiently by recursively testing multiple rows in parallel.  SURVEYMEMCON  A DRAM-transparent mechanism is developed based on the keyobservation that, in order to ensure correct operation of memory duringruntime, it is not required to detect and mitigate every possibledata-dependent failure that can potentially occur throughout the lifetime ofthe system. Instead, it is sufficient to ensure reliability againstdata-dependent failures that occur with only the current data content inmemory. Leveraging this observation, we propose MEMCON, a memorycontent-based detection and mitigation mechanism for data-dependent failures inDRAM. While the system and applications are running, MEMCON detects failureswith the current content in memory.

These detected failures are mitigated usinga high refresh rate for rows that contain the failing cells. MEMCONsignificantly reduces the mitigation cost as the number of failures withcurrent content is less than the total number of failures with every possiblecombination of data content. Using experimental data from real DRAM chipstested with real program content, we show that program data content in memoryexhibits 2.4X-35.2X fewer failures than all possible failures with any datacontent, making MEMCON effective in reducing mitigation cost.One critical issue with MEMCON is that whenever there is a writeto memory, content gets changed and MEMCON needs to test that new content todetermine if the new content introduces any data-dependent failures.Unfortunately, testing memory for data-dependent failures while the programsare simultaneously running in the system is expensive. Testing leads to extramemory accesses that can interfere with critical program accesses and can slowdown the running programs.

On the other hand, the benefit of testing comes fromusing a lower refresh rate once no failure is found in a row. The longer thecontent remains the same, the higher the benefit from the reduced refreshoperations.Therefore, there is a trade-off between the cost of testing vs. frequencyof testing. In this work, we show that the cost of testing can be amortized bythe reduction in refresh operations, if consecutive tests in a row areperformed at a minimum time interval. As testing is triggered by a writeoperation that changes the data content in memory, we refer to this minimuminterval as MinWriteInterval. We find that MinWriteInterval is 448–864 ms, dependingon the test mode, refresh rate, and DRAM timing parameters.We profile real applications and make a case for MEMCON with twoexperiments.

First, we demonstrate that a significant fraction of the timeprograms spend on intervals greater than MinWriteInterval (on average 71.8% ofthe execution time), which shows that MEMCON can amortize the cost of testingin real workloads. Second, we show that the impact of extra requests due to MEMCONis negligible on program performance (only 0.5-1.8% compared to the idealno-test case). We conclude that MEMCON is an effective and low-overhead onlinedetection and mitigation technique for data-dependent failures in DRAM.

This paper makes the following contributions: This is the first work topropose a system-level data-dependent failure detection and mitigationtechnique that is completely decoupled from the internal physical organizationof DRAM. Our detection and mitigation technique, MEMCON, depends only onthe current memory content of the applications. We analyze and model thecost and benefit of failure detection and mitigation with the current memorycontent. Our analysis demonstrates that the cost of testing for the currentcontent can be amortized if consecutive tests in a row are performed at a minimumtime interval. As testing needs to be performed when data content changes withprogram writes, we refer to this minimum interval as MinWriteInterval.

 Based on our analysis ofMinWriteInterval, we make a case for MEMCON with two experimental studies. Byprofiling real applications we show that (i) applications running in real machinesspend a significant amount of time on long write intervals, providing anopportunity to maximize the benefit of testing, and (ii) the impact of extrarequests due to MEMCON is negligible on program performance. PARBOROne way to uncover data-dependent DRAM failures at the systemlevel is to determine the location of physically neighboring cells in thesystem address space and use that information to devise test patterns thatensure that the physically neighboring cells are tested with the worst-case datapattern. This is a promising approach considering that each generation of chipscan have different address mappings, and a technique that can learn the mappingwill be generally applicable to any system with any chip.

As a cell isprimarily affected by two immediate neighbor cells, such a system-levelmechanism should detect the locations of these immediate neighbors.Unfortunately, naively ensuring that all two physically neighboring cells arecovered in testing requires exhaustively testing every combination of two bitaddresses in a row, an O(n2) test where n is the number of cells, which takes 49days of testing even for a single row with 8K cells. As cells get smaller and morevulnerable to cell-to-cell interference, it is likely that potentially moreneighboring cells will affect each other in the future 2, increasing the testtime to 1115 years for three neighbors and 9.1M years for four neighbors. Clearly,it is not feasible to run tests for such a long time to uncover data-dependentfailures. Our goal in this work is to propose a fast and efficient mechanism todetermine the locations of the physically neighboring cells in the systemaddress space. Doing so would help to detect data-dependent failures in thesystem and thus would enable techniques that improve DRAM reliability, latency,and energy, and aid DRAM technology scaling.To this end, we develop an efficient test method based on two keyideas.

The first key idea leverages the observation that cells exhibitvariability in the way they get affected by cell-to-cell interference. Eventhough cells get affected by both left and right neighbors, some cells are stronglycoupled to only one neighbor and fail when the data content of only one neighborchanges. We call these cells strongly coupled cells. Leveraging ourobservation, our key idea to reduce the test time is to locate the address of onlyone neighboring cell of strongly coupled cells. This approach reduces the testtime from O (n2) to O (n), as each address bit needs to be tested linearly onceto determine the address that causes the data-dependent failure in the stronglycoupled cell. However, detecting the address of only one neighbor can have anegative effect on the coverage of failures for weakly coupled cells, as thesecells depend on the content of both neighbors instead of one.

Our second keyidea enables us to detect both neighboring locations with multiple simplelinear tests. The idea is based on the observation that internal DRAMorganization is mostly regular and repetitive, with an abundance of parallelismin rows. Due to the regularity in internal DRAM address mapping, the distanceof the left neighbor in the system address space is the same for many cells inmultiple rows. Ditto for the distance of the right neighbor. And, due torandomness in process variation, some strongly coupled cells fail based on the contentof the left neighbor and some on the right neighbor. By running parallel tests indifferent rows simultaneously, we can detect the system address distance ofboth the left neighbor and the right neighbor for different strongly coupledcells, which together serve as the distances of the left and right neighborsfor weakly coupled cells (since internal DRAM address mapping is very regularacross rows). Consequently, it is possible to estimate the addresses of all neighboringcells by testing multiple cells in different rows simultaneously and aggregatingthe distances of the neighboring locations found in those rows.Based on these two key ideas, we propose PArallel Recursive neighBOR(PARBOR) testing, which detects the locations of physically neighboring cellsefficiently by recursively testing multiple rows in parallel.

We demonstratethe effectiveness of PARBOR by evaluating it using real DRAM chips. Using an FPGA-basedinfrastructure, we are able to find the locations of physically neighboringcells in 144 real DRAM chips manufactured by three major vendors with only 66?90tests, a 90X and 745,654X reduction, respectively, compared to tests with O(n) andO(n2) complexity. Using this neighboring cell location information, we devise anew test methodology, which performs only a small number of test iterations touncover data dependent failures in the entire chip. PARBOR uncovers 21.9% morefailures than a test with random data patterns that is unaware of the locationsof neighboring cells in 144 tested DRAM chips. We show that PARBOR enables not only prioroptimizations that rely on system-level detection of data-dependent failures, butalso new system-level optimizations that improve the reliability, performance,and energy efficiency of DRAM.

We propose and evaluate one such mechanism thatimproves DRAM performance by reducing refresh operations. We call this newrefresh reduction technique data content-based refresh (DC-REF). The key ideaof DC-REF is to employ a high refresh rate only in rows where the data contentof the application matches the worst-case pattern that causes failures. Ourevaluation shows that DC-REF reduces the number of refreshes by 73% andimproves performance by 18% for a system with 32 Gbit DRAM chips and 8 coresrunning a wide range of applications.

This paper makes the following contributions:• This is the first work to propose an efficient system-level mechanismfor locating the addresses of neighboring cells in DRAM devices. Our mechanism,PARBOR, reduces the test time for such detection by exploiting the notion of stronglycoupled cells and recursively testing multiple rows in parallel. We use theaddresses of physically neighboring cells to devise a new test methodology thatcan efficiently uncover data-dependent failures.• We experimentally demonstrate that PARBOR can detect theneighboring cell locations with a small number of tests.

Using an FPGA-basedinfrastructure, we show that PARBOR detects neighboring locations with only 66?90tests in 144 real DRAM chips from three major manufacturers, a 90X and 745,654Xreduction compared to optimized/naïve tests, with respectively O(n) and O(n2) complexity.• We show that PARBOR uncovers, on average, 21.9% more failuresthan a test with random data patterns that is unaware of the locations ofneighboring cells.• We show that PARBOR enables new mechanisms to improve futurememory systems. Based on the detected patterns that cause failures in cells, wepropose a data content-based refresh minimization mechanism, DC-REF, whichimproves performance by 18% for a system with 32 Gbit DRAM chips and 8 coresover a wide range of applications.                    CONCLUSION We introduce MEMCON, the firstsystem-level detection and mitigation technique for data-dependent DRAMfailures that completely decouples failure detection from internal DRAMorganization. MEMCON detects failures with the current content in memory byrunning online testing simultaneously with program execution. In this work, wemake a case for MEMCON, showing that the overhead of such a concurrentdetection technique can be negligible.

We believe that our analysis andexperimental results will inspire future works to design, build, and evaluatememory content-based detection and mitigation techniques in real systems. We introduced PARBOR, an efficientsystem-level technique that 1) determines the locations of physicallyneighboring cells in DRAM and 2) uses this information to uncover datadependent failures. PARBOR greatly reduces the test time required to determinephysically neighboring cells by exploiting1) Our new observation that some DRAMcells are strongly affectedby only one of their neighbors and 2)the regularity and abundant parallelism found in modern DRAM chips. To our knowledge,this is the first work to provide a fast and practical method to detectdata-dependent DRAM failures at the system level, in the presence of scramblingof addresses within DRAM.We experimentally demonstrate theeffectiveness of PARBOR using a large number of real DRAM chips. PARBOR greatlyreduces the number of tests (by orders of magnitude) while uncovering significantlymore data-dependent failures than state of the-art testing methods. We demonstratethat PARBOR enables both previously-proposed and new techniques that improve DRAMreliability, performance and energy efficiency. We introduce the notion of DataContent-based REFresh (DC-REF) as one example new technique, and show that itsignificantly improves system performance.

We hope that PARBOR will also inspirethe development of a wide range of new system-level mechanisms that takeadvantage of efficient dynamic detectionof data-dependent DRAM failures.  REFERENCE·      A Case for MemoryContent-Based Detection and Mitigation of Data-Dependent Failures in DRAMSamira Khan, ChrisWilkerson, Donghyuk Lee, Alaa R. Alameldeen and OnurMutlu ·      PARBOR: An EfficientSystem-Level Technique to Detect Data-Dependent Failures in DRAMSamira Khan, DonghyukLee and Onur Mutlu

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